The Cached DRAM Binary CAM (CDBCAM) core CDBCAM core is a member of the family of CAMs provided by AMD. The family consists of the following members:
- Binary CAM (BCAM)
- Used for exact matching, BCAM is available in two versions. A software-managed version and a hardware-managed version (CBCAM). CBCAM offers you the flexibility to insert or delete entries using a hardware interface with or without a software driver. For more information, see Binary CAM Search LogiCORE IP Product Guide (PG317).
- Cached DRAM Binary CAM (CDBCAM)
- Used for exact matching, CDBCAM is similar to BCAM except that it uses DRAM as the primary storage for entries, whereas BCAM uses URAM or block RAM (BRAM). CDBCAM can store more entries, and, in combination with its on-chip BCAM cache, it can achieve lookup rates comparable to the BCAM. Similar to the BCAM, the CDBCAM supports both a software managed and hardware managed interface. For further information, see Cached DRAM Binary CAM LogiCORE IP Product Guide (PG427).
- Semi TCAM (STCAM)
- Described in this document. It is also available in two versions, one with fixed rate and latency and the other with variable rate and latency for low-cost applications. The low-cost version supports ranges to avoid costly entry explosion to cover ranges. The STCAM is fully flexible in terms of number, size and position of wildcard (ignored) fields. Every key bit has a corresponding mask bit. The number of allowed unique masks is however limited. This allows for considerable memory and logic optimizations. For LPM applications, the LPM mode of the variable rate STCAM uses special HW to compress keys which improves storage efficiency. The LPM mode uses prefix masks instead of fully flexible masks which allow for more masks at a lower cost.
- DRAM Semi-Ternary CAM (DSTCAM)
- DSTCAM is similar to STCAM except that it uses DRAM for storage of entries. The DSTCAN is flexible in terms of number, size, and position of wildcard fields. Every key bit has a corresponding mask bit. The number of allowed masks is however limited. This allows for considerable memory and logic optimizations. For LPM applications, the DSTCAM uses special hardware to compress keys which improves storage efficiency. The LPM mode uses prefix masks rather than fully flexible masks that reduces cost. See the DRAM Semi-Ternary CAM LogiCORE IP Product Guide (PG468).
- Ternary CAM (TCAM)
- The primary usage of TCAM is tables requiring full flexibility in terms of size and position of wildcard (ignored) fields. Every key bit has a corresponding mask bit stored together with the key. All entries can have different masks. TCAMs are used for Access Control List (ACL) type of lookups, requiring a large number of different masks. See the Ternary CAM Search LogiCORE IP Product Guide (PG318).
The Cached DRAM Binary CAM (CDBCAM) core is related to the on-chip BCAMs provided by AMD, see Binary CAM Search LogiCORE IP Product Guide (PG317). The main difference is that CDBCAM uses DRAM as a primary storage for entries, whereas on-chip BCAM uses FPGA internal SRAM. The CDBCAM can store orders of magnitude more entries, and, in combination with an optional BCAM cache implemented as an on-chip BCAM, can achieve lookup rates comparable to the on-chip BCAM.
Only AMD Versal™ architecture is supported. Support for HBM, DDR4, DDR5, and LPDDR5 DRAM types.
The CDBCAM stores {key, response} entries
in DRAM. The Lookup interface of the CDBCAM
receives a lookup key and outputs a result that
indicates if the lookup key matches the key of any entry in the CDBCAM. If any CDBCAM entry is matched, the
response value of the matching entry is output.
Otherwise, the default software programmable response
value is output.
The entries are read and written using a set of high-level API functions. The API functions are written in C and delivered as part of the IP. The API encapsulates the details of memory management and register access and provides a simple and efficient management interface. The API software with detailed documentation is found in the CAM IP Product Page. You must add a basic hardware read and write functions to the end of the driver file. This allows for a portable communications link between the API software and the hardware. For instance, the communication link could be AXI4-Lite or PCIe® . You can choose to enable HW-assisted CAM management to reduce the CPU memory and processing footprint.
A CDBCAM design is highly configurable at compile time, which makes it suitable for a large variety of applications. The following table lists the configuration parameters.
| Parameter Name | Values | Description |
|---|---|---|
| CLOCKING_MODE | SINGLE_CLOCK / DUAL_CLOCK | The use of a separate memory clock is optional. In SINGLE_CLOCK mode all logic (except a small amount of control logic on the AXI4-Lite domain) is clocked on the lookup interface clock. |
| LOOKUP_INTERFACE_FREQ | 15-400 MHz | Frequency of the lookup request interface. In both SINGLE_CLOCK and DUAL_CLOCK mode, the maximum frequency supported is 400 MHz. |
| MEMORY_INTERFACE_FREQ | 15-400 MHz | Frequency of the memory interface in
DUAL_CLOCK mode. ≤ LOOKUP_INTERFACE_FREQ |
| DRAM_TYPE | HBM, DDR4, LPDDR5 | DRAM type. The selection also determines the NoC NMU width (32B for HBM, and 64B for other types). |
| NUM_ENTRIES | 8K-60M | Number of entries that can be stored in CDBCAM IP. |
| KEY_WIDTH | 10-992 |
Key width in bits. The width of the lookup key. KEY_WIDTH + RESPONSE_WIDTH cannot exceed 1007. |
| RESPONSE_WIDTH | 1-997 | Response width in bits. The width of
the lookup response. KEY_WIDTH + RESPONSE_WIDTH cannot exceed 1007. If the KEY_WIDTH + RESPONSE_WIDTH < 496, then each entry will take 64B of DRAM, otherwise it will take 128B. |
| DEFAULT_RESPONSE_VALUE | Any value of RESPONSE_WIDTH bits | User defined default response in case of no match. |
| MEMORY_PRIMITIVE | ULTRA, BLOCK | Memory type for storing cache entries. |
| CACHE_SUPPORT | NONE, QUARTER, HALF, FULL |
Cache support can be disabled, or, when enabled, use different memory types and maximum lookup rate as follows.
|
| UPDATE_MODE | SOFTWARE, HARDWARE | Table management when performed by software requires a shadow memory and performance depends on the processor. On the contrary in hardware mode no additional memory is required, and performance is independent of the processor, but needs extra hardware resources. However, insert, delete, and update operations are triggered by software in hardware mode. |
| NUM_PCS | 1,2,4,8 | Only applicable for HBM. The default value is set in the GUI and calculated based on NUM_ENTRIES, KEY_WIDTH and RESPONSE_WIDTH. The default value calculation tries to minimize the number of PCs. The default value can be changed to use more but not fewer PCs. If the number of PCs is increased the memory BW increases and also the lookup rate. If more PCs are used, the memory usage per PC is automatically reduced. |
| NUM_NOC_NMU_IF | 1,2,4,8 | The number of NoC NMUs to use to connect CDCAM to the NoC. When the DRAM_TYPE parameter is set to DDR this is fixed to 1 (and the parameter is hidden). When DRAM_TYPE is set to HBM this can vary. Generally, values equal to the number of PCs, twice the number of PCs and half the number of PCs are allowed. A recommended value is suggested when the number of PCs is selected, this will give best performance while minimizing LUT count. |
| DEDICATED_PC | True/False | When checked, this allows the table
to expand to fill PCs (even if the table is smaller than the size of the
PC). This should be used if the PC is not shared with any other process.
This option will give better lookup performance when the table is filled
to the desired number of entries, and also better insert performance
when close to full. The required DRAM size depends on this option and it is updated in the GUI when the parameter is modified. If the table is smaller than a PC and this option is enabled, then the required DRAM size increases to PC size. |
| OVERRIDE_PC | True/False | Determined by the entry size and the number of entries, the GUI feeds back the minimum amount of required HBM PCs. When the OVERRIDE_PC parameter is enabled, you can increase the number of PCs to achieve higher lookup rates. |
| OVERRIDE_NMU | True/False | Based on the selected number of PCs, the GUI feeds back the optimal number of NoC NMUs. When the OVERRIDE_NMU parameter is enabled, you can decrease the value of NMUs for better resource utilization or increase the value of NMUs for a potential higher lookup rate. |
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There are two options for configuration parameters:
- All of these parameters are extracted or calculated from the P4 code during compilation. Vitis Networking P4 ensures that the parameters used to generate the hardware CDBCAM and those used to create the software CDBCAM are synchronized.
- For standalone usage, you must guarantee that the parameters used to generate the hardware CDBCAM and the parameters used to call the software CDBCAM are identical. The hardware and software example designs both have examples of how to setup the instance of the software driver for a particular parameterization of the IP. See Example Design and Software Application Example Design.
DDR4 and LPDDR5 support single channel only. For HBM, it is possible to use multiple HBM PCs, see Example Design for more details.