For details, see the Vivado Design Suite User Guide: Designing with IP (UG896).
Note: When the CDBCAM IP example design is generated, a simulation SystemVerilog
package file is also created with the name
<instance-name>_sim_pkg.sv. This file contains the configuration settings
used for this particular CDBCAM IP instance. You
can use this simulation package file and the SystemVerilog tasks found therein in your test
bench, if desired.