Memory Specification Tab - Memory Specification Tab - 2.0 English - PG427

DRAM Memory Type

Choice of HBM, DDR4, or LPDDR5 (device dependent). Determines the memory controller connected to the NoC. DDR4 and LPDDR5 uses one AXI MEM port of 512 bit data width while HBM uses two or more AXI MEM ports of 256 bit data width.

Number of PCs

Determined by key width, response width, and number of entries. For HBM, the number of PCS can be increased above the minimum.

Modify minimum PCs

Modify the minimum number of PCs for better performance.

Dedicated PC

Use if not sharing HBM PCs with other blocks for higher lookup rate. When enabled, if the table footprint of entries is smaller than the selected number of PCs, the table footprint are expanded to fill the available space. Otherwise, only the table footprint based on number of entries are occupied.

Number of NoC NMUs

The number of NoC NMU interfaces used for DDR. When HBM is used, the number of NoC NMU interfaces can be customised. Allowed NMUs are PCs x 0.5, PCs x 1, and PCs x 2.

Customize NoC NMUs

Customise the default number of NoC NMUs for better resource utilisation.

Required DRAM Size

This is not a configurable parameter, but it provides a calculation of the minimum DRAM size required to fulfil the number of entries entered, with the key and response widths considered.

DRAM Size per PC

This is not a configurable parameter, but it provides the DRAM size required for the current configuration per PC.

Cache Configuration

Using a cache in CDBCAM results in a higher average lookup rate (see Performance) and lower latency for systems that benefit from caching (that is, when the frequency of lookups for some keys are much higher than for the others). This improvement comes at the cost of FPGA resources. You can choose not to use the cache, or when using it, to choose between different options that are determined by the required lookup rate and FPGA resource cost. The reference point in the case of the lookup is the AXI4S clock key_clk frequency. You can determine the lookup rate to be full, half, or a quarter of that frequency. You can also choose whether to use URAM or block RAM memory primitives for cache storage. In the case of URAM, full rate builds a cache that can store up to 16K entries, 8K for half rate and 4K for quarter rate. When block RAM is used these sizes are eight times smaller respectively.