- Associative array containing arbitrary (key, response) entries.
- Exact match key lookup returns hit/miss result and associated response value on hit.
- High throughput, which includes one lookup per clock cycle up to 400 Mlps for cached entries, and up to 200 Mlps for entries that have not been cached.
Note: Achievable clock frequencies depend on the device
being used, logic resource and routing congestion and the resources used by the CAM on-chip
memory.
- Flexible, supporting a wide range of key widths, response widths and lookup rates with optimized resource utilization.
- Supports all key widths up to 992 bits and all response widths up to 997 bits.
- Supports tables with millions of entries using DRAM storage: HBM, DDR4, and LPDDR5.
- Supports up to eight Pseudo Channels (PCs) of Versal HBM.
- High bandwidth connection to DRAM using Network on Chip (NoC), up to two NoC Controller Units per memory channel.
- Supports URAM/block RAM implementations for cache on-chip memory.
- High storage efficiency. Approximately 90% of the RAM bits are transformed to CAM bits.
- Supports entry insert, delete, and update using highly portable software APIs.
- Support choice between SW and HW control for entry insert, delete, and update.
- Supports AMD Vivado™ IP integrator.