CDCAM Specification Tab - CDCAM Specification Tab - 2.0 English - PG427

Component Name

The name of the core component to be instantiated. The name must begin with a letter and be composed of the following characters: a to z, A to Z, 0 to 9 and ‘_’.

The CDBCAM IP core configuration fields are shown in the following figure, and are defined below.

Figure 1. CDCAM Specification

CDCAM Mode

The pull-down menu options are: BCAM and STCAM. Depending on the option selected, the available configuration parameters vary.

BCAM

Selects the Binary Content Addressable Memory (BCAM) described in this document.

STCAM

Refer to DRAM Semi-Ternary CAM LogiCORE IP Product Guide (PGTBD).

Update Mode

In situations where access to a powerful CPU with lots of available memory is not available, hardware controlled content update can be a good choice. It requires little CPU power and memory, as the full execution of inserts, updates, and deletes is performed by hardware. This comes at a cost in FPGA resources.

Number of Entries

Enter the number of key/response entries that you want in the CDBCAM (depth). The range is from 8192 to 60397977 entries although there are limitations within that range depending on other parameter choices made. Default is 1887436 (approx. 90% of 2M).

Table 1. Limitations

DRAM_TYPE	Versal Device Type	Entry size (KEY_WIDTH + RESPONSE_WIDTH ) < 512	NUM_ENTRIES range
DDR4	any	Yes	8192 – 60,397,977
DDR4	any	No	8192 – 60,397,977
HBM	xcvh1582, xcvh1782	Yes	8192 – 60,397,977
HBM	xcvh1582, xcvh1782	No	8192 – 60,397,977
HBM	xcvh1522, xcvh1542, xcvh1742 1	Yes	8192 – 60,397,977
HBM	xcvh1522, xcvh1542, xcvh1742 1	No	8192 – 30,198,988
These devices have 512 MB per PC, thus have the limitation for number of large size entries.

Note: When stored in DRAM, entry size (key width plus response width plus one status bit) is rounded up to the nearest round number of bits – 512 or 1024. The maximum number of entries in the CDBCAM is a key configuration parameter to set. When NUM_ENTRIES is set, it is important to know the following:

1. Up to 90% of available memory can be used for storing the entries.
2. Dedicated DRAM size will be rounded up to the nearest power of 2.

For example:

For entry size of 453b, each entry would take 512b (64B) of DRAM space. If the required number of entries is 7 million, the occupied DRAM space will be at least 64B x 7 x 10^6 / 90% = 497,777,778. When rounded up to the nearest power of 2, dedicated DRAM size must be at least 512MB.

Key Width

The width (unpadded) of the key value in bits. The default is 64 bits wide. The range is 10 to 992 inclusive.

KEY_WIDTH + RESPONSE_WIDTH should not exceed 1007.

Response Width

The width (unpadded) of the response value in bits. Default is 64 bits wide. Range is 1 to 997 inclusive.

KEY_WIDTH + RESPONSE_WIDTH should not exceed 1007.

Default Response

When a lookup misses, the value set in this parameter is the output. Width of parameter corresponds with RESPONSE_WIDTH.