LogiCORE™ IP Facts Table | |
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Core Specifics | |
Supported Device Family |
Zynq®
UltraScale+™
RFSoC Gen 1/Gen 2/Gen 3 Zynq UltraScale+™ RFSoC DFE Zynq UltraScale+ |
Supported User Interfaces | AXI4, AXI4-Lite, and AXI4-Stream |
Provided with Core | |
Design Files | Local Vivado® repository |
Example Design | Please contact your local Xilinx sales representative for more information. |
Test Bench | Please contact your local Xilinx sales representative for more information. |
Constraints File | Please contact your local Xilinx sales representative for more information. |
Simulation Model | Not Provided |
Supported S/W Driver | Executable and linkable format files are now packaged along with the DFE Subsystem Reference Design which need to be downloaded separately. |
Tested Design Flows | |
Design Entry | Vivado Design Suite 2022.2 |
Simulation | Not Provided |
Synthesis | Vivado Synthesis |
Support | |
All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
Xilinx Support web page | |
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