| Core
Specifics |
| Supported Device Family
1
|
AMD Versal™
adaptive SoC, AMD UltraScale+™
, AMD Zynq™ 7000, AMD Virtex™ 7, AMD Kintex™ 7
|
| Supported User Interfaces |
AXI4-Stream
|
| Resources |
Performance and Resource Use web
page
|
| Provided with Core |
| Design Files |
Verilog |
| Example Design |
Verilog
4
|
| Test Bench |
Verilog |
| Constraints File |
Xilinx Design Constraints (XDC) |
| Simulation Model |
Source HDL with SecureIP transceiver simulation models |
| Supported S/W Driver
2
|
N/A |
| Tested Design Flows
5
|
| Design Entry |
AMD Vivado™ Design Suite
|
| Simulation |
For supported simulators, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973). |
| Synthesis |
Vivado Synthesis |
| Support |
| Release Notes and Known Issues |
Master Answer Record: 21263
|
| All Vivado IP Change Logs |
Master Vivado IP
Change Logs: 72775
|
|
Support web
page
|
- For a complete list of supported devices, see
the AMD Vivado™
IP catalog.
- For more information on supported device
family, see References.
- For more complete performance data, see Performance.
- The IP core is delivered as Verilog source
code. A mixed-language simulator is required for example design simulation because
of subcore dependencies.
- For the supported versions of the tools, see the
AMD Vivado™ Design Suite User Guide: Release Notes,
Installation, and Licensing. Refer to
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
|