Aurora 64B/66B Duplex - Aurora 64B/66B Duplex - 12.0 English - PG074

Aurora 64B/66B LogiCORE IP Product Guide (PG074)
Document ID
PG074
Release Date
2023-11-17
Version
12.0 English

During the board power-on sequence, both the pma_init and reset_pb signals are expected to be High. INIT_CLK and GT_REFCLK are expected to be stable during power-on for the proper functioning of the Aurora 64B/66B core. When both clocks are stable, pma_init is deasserted followed by the deassertion of reset_pb.

Aurora 64B/66B Duplex Power On Sequence

Figure 1. Aurora 64B/66B Duplex Power On Reset Sequence

Aurora 64B/66B Duplex Normal Operation Reset Sequence

Figure 2. Aurora 64B/66B Duplex Normal Operation Reset Sequence

Reset Sequencing

  1. Assert reset_pb. Wait for a minimum time equal to 128*user_clk's time-period.
  2. Assert pma_init. Keep pma_init and reset asserted for at least one second to prevent the transmission of CC characters and ensure that the remote agent detects a hot plug event.
  3. Deassert pma_init.
  4. Deassert reset_pb. (full stop) Internally the logic waits for user_clk to get stable and deasserts sys_reset_out after which reset_pb can be deasserted.