The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 07/13/2022 Version 1.6 | |
| General updates | Updated the register map ZIP file link |
| 07/07/2022 Version 1.6 | |
| General updates | Updated with minor technical changes |
| 01/10/2022 Version 1.5 | |
| PTP 1588 Timer Syncer IP | Added PTP TIMESTAMP and SYSTIMER BUS information |
| Register Spaces | Updated Register Map |
| 11/15/2021 Version 1.4 | |
| Product Specification |
|
| Example Design | Updated Example Design |
| Design Flow Steps | Updated for v1.4 |
| 02/05/2021 Version 1.3 | |
| GT Quad Integration with Xilinx IP Cores | Added new section under Design Flow Steps |
| 02/03/2021 Version 1.3 | |
| Initial release. | N/A |