Reset Port Description - 1.6 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

Document ID
PG314
Release Date
2022-07-13
Version
1.6 English

Reset pins and RESET_REG bits other than tx_core_reset, rx_core_reset, tx_serdes_reset, and rx_serdes_reset are for debugging purpose only. It should not be asserted by the user logic.

Table 1. Reset Port Description
MRMAC Reset Pin Associated RESET_REG Bits (Per Port) Description
rx_core_reset[3:0]

tx_core_reset[3:0]

rx_core_reset

tx_core_reset

Per-port TX and RX core reset.

Asserting the reset resets the entire RX or TX datapath for that port including:

  • SerDes interface logic
  • Status registers
  • AXI4-Stream user interface
  • Flex I/F
  • System Timer interface and logic
rx_serdes_reset[3:0] rx_serdes_reset[N:0] Per-port RX SerDes (GT) interface reset.

The RX SerDes can be reset through the register interface on a per-port basis. However, different ports have different allowable configurations and hence there are different reset fields depending on the port. Consequently, each port's RESET_REG has an N-bit rx_serdes_reset field, where N represents the number of PHY lanes present for a Port's configuration.

For example, Port 0 can support operation up to and including 100G (requiring four SerDes) and so the reset field is four bits wide. However, if the port were to be configured as 50G, only rx_serdes_reset[1:0] would be in use.

Meanwhile, Port 1 only supports lower speed operation and so it is directly tied to a SerDes instance. Therefore, there is only one active reset bit (rx_serdes_reset[0]).

tx_serdes_reset[3:0] tx_serdes_reset Per-port TX SerDes (GT) interface reset.

A single reset port resets each of the TX GT interface logic. For example, tx_serdes_reset[0] resets all of the GT interface logic for Port 0, regardless of configuration.

apb3_preset Resets the AXI4-Lite port logic, status, and statistics registers.

The clock and reset connection between MRMAC and GT is shown in the following figure.

Figure 1. MRMAC and GT Clock and Reset Architecture