Receive Clocks - 1.6 English

The following describes the receive clocks in the MRMAC.

rx_serdes_clk[3:0]

This GT SerDes clock is used to drive data across the SerDes interface to the MRMAC.

rx_core_clk[3:0]

This is the internal high-speed clock which drives the bulk of the MRMAC receive datapath. This per-port clock is typically shared with the tx_core_clk[3:0], but depending on the application it can be derived from the rx_serdes_clk.

rx_alt_serdes_clk[3:0]

This is an internally-used clock derived from the primary SerDes clocks. These clocks run at exactly 1/2 the rx_serdes_clk[3:0] frequencies. The logic and hook-ups for this clock are typically generated by the IP Wizard.

rx_flexif_clk[3:0]

This is used by the flex interface. When the Flex I/F is active and in a multi-lane mode (that is, data rate > 25G), rx_flexif_clk[N] must operate at a frequency ≥ 1/2 of the corresponding rx_core_clk[N] frequency. When the flex interface is in a single lane mode (25G or 10G), it must run at a frequency ≥ 1/2 of the corresponding rx_serdes_clk[N] frequency.

rx_axi_clk[2][0]

This is a per-port AXI clock. In addition to clocking the RX AXI4-Stream interface in independent clocking mode, the rx_axi_clk[2][0] clocks are also used only to clock certain statistics and flow control signals. The rx_axi_clk[2][0] clocks must operate at a frequency high enough to maintain the desired data rate across the AXI4-Stream bus, which means rx_axi_clk[N] must be greater than or equal to 1/2 of the corresponding rx_core_clk[N] (or rx_serdes_clk[N] in 10GE or 25GE mode) frequency.

The minimum values for the rx_axi_clk[2][0] clocks for the various modes of operation match the table listed for the tx_axi_clk.

rx_ts_clk[3:0]

This clock drives the 1588 timestamping signaling. The MRMAC timestamp timers attempt to synchronize with the external time-of-day source which is running on this clock.