Address translation between the CDBCAM and
external memory must be performed by the NoC. For example, for a design with DDR memory
the incoming address (0x0) from CDBCAM could
be remapped into DDR address region starting at 0x8_0000_0000.
The range for address remap should also be configured as per the required DRAM physical size for the design.
For designs involving HBM with multiple PCs, you should configure address remap for all channels. Generally, it should be a case of mapping a single PC to each NMU. When two NMUs are assigned to each PC then that PC should be mapped to each. When a single NMU is assigned to each PC then that PC should be mapped. When a single NMU is assigned to two PCs (that is, the ratio of PCs to NMUs is 2:1), then both PCs need to be mapped to each NMU.
When using non-dedicated PCs the same mapping applies but only the relevant section of the PC is required to be mapped.
The Example Design section gives an example of the NoC mapping required.
For more details see Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).