|
Core Specifics |
| Supported Device Family
1
|
AMD Versal™
adaptive SoC,
AMD Versal™ HBM series. |
| Supported User Interfaces |
AXI4-Lite, AXI4-Stream. |
| Resources |
Performance
|
| Provided with
Core
|
| Design Files |
Encrypted Verilog RTL |
| Example Design |
Verilog |
| Test Bench |
Verilog |
| Constraints File |
Xilinx Design Constraint (XDC) |
| Simulation Model |
Verilog source code |
| Supported S/W Driver
|
Standalone / Vitis Networking P4 |
| Tested Design
Flows
2
|
| Design Entry |
Standalone, Vitis Networking P4, AMD Vivado™
IP integrator |
| Simulation |
VCS |
| Synthesis |
Vivado Synthesis |
| Support |
| All Vivado IP Change Logs |
Master Vivado IP Change Logs:
72775
|
|
Support web
page
|
- For a complete list of supported devices, see
the AMD Vivado™
IP catalog.
- For the supported versions of third-party
tools, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
|