Example Design - 1.2 English - PG427

Cached DRAM Binary CAM LogiCORE IP Product Guide (PG427)

Document ID
PG427
Release Date
2024-11-27
Version
1.2 English

The following sections show the example design block designs for both DDR and HBM:

DDR Memory

Figure 1. CDBCAM Example Design for DDR Memory Generated by Your Tool

Address translation between CDBCAM and DDR memory is performed by axi_noc_0.

The configuration depicted in the following figure could be used as a reference for remapping.

Figure 2. Remapping Reference (DDR)

HBM

Figure 3. CDBCAM Example Design for HBM Generated by Your Tool

Address translation between CDBCAM and HBM is performed by axi_noc_0.

The configuration depicted in the following figure could be used as a reference for remapping.

Figure 4. Remapping Reference (HBM) for Two PCs and Four NMUs Generated by Your Tool
Figure 5. Remapping Reference (HBM) for Four PCs and Two NMUs Generated by Your Tool
Figure 6. Remapping Reference (HBM) for Four PCs and Four NMUs Generated by Your Tool