All timing analysis has been performed on -2M speed grade. The CDBCAM clock domains are shown in the following table.
| Clock | Max. Frequency | Description |
|---|---|---|
| s_axi_aclk | 150 MHz | This clock is used for table management. The AXI management interface has a completely asynchronous relationship with the lookup interface. |
| key_clk | 400 MHz | The rest of the CDBCAM logic including Lookup Request/Response interface and its related logic. |
| mem_clk | 400 MHz | NoC interface and its related logic. Note: 250 MHz is a reasonable target. Values higher than this can be challenging and
depend on key-size, DRAM options, and device speed-grade.
|