The synchronous TX AXI4-Stream interface accepts packets of arbitrary
length. All signals are synchronous relative to the rising-edge of the
c0_axi_clk clock. The following figure shows a sample waveform for
data transactions for two consecutive 65-byte packets using a 512-bit segmented bus.
Each of the four segments is 128 bits wide.
Data is transferred on a given tx_axis_tdata<M> segment when the corresponding tx_axis_tuser_ena<M> is asserted. The tx_axis_tuser_ena<M> signal qualifies other inputs of
segment <M> and must be valid every c0_axi_clk
clock cycle. When tx_axis_tuser_ena<M> is
deasserted, other signals of segment <M> are ignored.
The start of a packet is identified by the assertion of tx_axis_tuser_sop<M> with the corresponding tx_axis_tuser_ena<M>. Similarly, the end of a packet is identified
by the assertion of tx_axis_tuser_eop<M> with the
corresponding tx_axis_tuser_ena<M>. Both tx_axis_tuser_sop<M> and tx_axis_tuser_eop<M> can be asserted on a given cycle. This occurs
for packets that are less than or equal to the AXI4-Stream bus width. Furthermore, both tx_axis_tuser_sop<M> and tx_axis_tuser_eop<M> can be asserted for a given segment on a given
cycle. This occurs for packets that are less than or equal to 16 bytes (the segment
size).
The channel number for a packet is presented on the tx_axis_tuser_chan<M> input of the corresponding segment and must be
valid for every segment where tx_axis_tuser_ena<M> is asserted. After SOP has been asserted for a
certain channel number, it cannot be asserted again with that channel number until EOP
has been asserted for the same channel number.
The first 16 bytes of a packet must be presented on a given tx_axis_tdata<M> segment during the cycle that the
corresponding tx_axis_tuser_sop<M> and tx_axis_tuser_ena<M> are asserted. In other words,
the SOP is segment aligned. Subsequent 16-byte chunks of data are transferred during
segments that follow. For each of those segments, the corresponding tx_axis_tuser_sop<M> must be negated. The first byte
of the packet is written on bits [127:120] of the segment, the second byte on bits
[119:112], and so forth.
tx_axis_tdata<M> segment whose corresponding tx_axis_tuser_eop<M> is asserted. Unless tx_axis_tuser_eop<M> is asserted, all 16 bytes of tx_axis_tdata<M> must contain valid data whenever
tx_axis_tuser_ena<M> is asserted. tx_axis_tuser_chan<M> input identifies the
packets from different channels.During the segment containing the last bytes of a packet, the tx_axis_tuser_mty<M> port reflects how many bytes of
the corresponding tx_axis_tdata<M> are invalid
(or empty). A given tx_axis_tuser_mty<M> port
only has meaning during cycles when both the corresponding tx_axis_tuser_ena<M> and tx_axis_tuser_eop<M> are asserted. If tx_axis_tuser_mty<M> has a value of 0x0, there are no empty byte lanes (that is, all bits of the segment are
valid).
If tx_axis_tuser_mty<M> has a value of
0x1, then one byte lane is empty — specifically
tx_axis_tdata<M>[7:0] does not contain valid
data.
If tx_axis_tuser_mty<M> has a value of
0x2, then two byte lanes are empty — specifically
tx_axis_tdata<M>[15:0] does not contain valid
data.
If tx_axis_tuser_mty<M> has a value of
0x3, then three byte lanes are empty — specifically
tx_axis_tdata<M>[23:0] does not contain valid
data. And so forth for other possible values of tx_axis_tuser_mty<M>.
During the segment containing the last bytes of a packet, when tx_axis_tuser_eop<M> is asserted with tx_axis_tuser_ena<M>, the corresponding tx_errin<M> can also be asserted. This marks the
packet as being in error and this information is included in the final Interlaken
Control Word associated with this packet. When tx_axis_tuser_eop<M> and tx_errin<M> are sampled as 1, the value of tx_axis_tuser_mty<M>[2:0] is ignored and treated as equal to 000, while tx_axis_tuser_mty<M>[3] is used as usual.