Transceiver Interface Bit Ordering (core_mode 0x3)

Transceiver Interface Bit Ordering (core_mode 0x3) - 1.2 English

Versal ACAP Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)

Document ID

PG371

Release Date

2023-01-19

Version

1.2 English

When operating in ILKN mode (with or without FEC) and the ctl_core_mode[1:0] field of the CFG_CORE_MODE_REG register is set to 0x3, the bit ordering for all lanes is as described in the following tables.

Table 1. TX ILKN Bit Ordering Summary (core_mode = 0x3)
ILKN Lane	ILKN Lane for Stats	ILKN Output core_mode¹ = 0x3 intf_mode² = 0x3 gearbox_mode³ = 0x1,0x2	ILKN Output core_mode¹ = 0x3 intf_mode² = 0x2 gearbox_mode³ = 0x1,0x2
0	0	tx_serdes_data0[79:0] tx_serdes_data1[79:0]	tx_serdes_data0[79:0]
1	1	tx_serdes_data2[79:0] tx_serdes_data3[79:0]	tx_serdes_data1[79:0]
2	2	tx_serdes_data4[79:0] tx_serdes_data5[79:0]	tx_serdes_data2[79:0]
3	3	tx_serdes_data6[79:0] tx_serdes_data7[79:0]	tx_serdes_data3[79:0]
4	4	tx_serdes_data8[79:0] tx_serdes_data9[79:0]	tx_serdes_data4[79:0]
5	5	tx_serdes_data10[79:0] tx_serdes_data11[79:0]	tx_serdes_data5[79:0]
6	12	tx_serdes_data12[79:0] tx_serdes_data13[79:0]	tx_serdes_data6[79:0]
7	13	tx_serdes_data14[79:0] tx_serdes_data15[79:0]	tx_serdes_data7[79:0]
8	14	tx_serdes_data16[79:0] tx_serdes_data17[79:0]	tx_serdes_data8[79:0]
9	15	tx_serdes_data18[79:0] tx_serdes_data19[79:0]	tx_serdes_data9[79:0]
10	16	tx_serdes_data20[79:0] tx_serdes_data21[79:0]	tx_serdes_data10[79:0]
11	17	tx_serdes_data22[79:0] tx_serdes_data23[79:0]	tx_serdes_data11[79:0]
core_mode refers to `ctl_core_mode[1:0]`. intf_mode refers to `c0_ctl_tx_serdes_intf_mode[1:0]`. gearbox_mode refers to `c0_ctl_tx_gearbox_mode[1:0]`.

Table 2. RX ILKN Bit Ordering Summary (core_mode = 0x3)
ILKN Lane	ILKN Lane for Stats	ILKN Output core_mode¹ = 0x3 intf_mode² = 0x3 gearbox_mode³ = 0x1,0x2	ILKN Output⁴ core_mode¹ = 0x3 intf_mode² = 0x2 gearbox_mode³ = 0x1,0x2	ILKN Output⁵ core_mode¹ = 0x3 intf_mode² = 0x2 gearbox_mode³ = 0x1,0x2
0	0	rx_serdes_data0[79:0] rx_serdes_data1[79:0]	rx_serdes_data0[79:0]	rx_serdes_data0[79:0]
1	1	rx_serdes_data2[79:0] rx_serdes_data3[79:0]	rx_serdes_data1[79:0]	rx_serdes_data1[79:0]
2	2	rx_serdes_data4[79:0] rx_serdes_data5[79:0]	rx_serdes_data2[79:0]	rx_serdes_data2[79:0]
3	3	rx_serdes_data6[79:0] rx_serdes_data7[79:0]	rx_serdes_data3[79:0]	rx_serdes_data3[79:0]
4	4	rx_serdes_data8[79:0] rx_serdes_data9[79:0]	rx_serdes_data4[79:0]	rx_serdes_data4[79:0]
5	5	rx_serdes_data10[79:0] rx_serdes_data11[79:0]	rx_serdes_data5[79:0]	rx_serdes_data5[79:0]
6	12	rx_serdes_data12[79:0] rx_serdes_data13[79:0]	rx_serdes_data12[79:0]	rx_serdes_data6[79:0]
7	13	rx_serdes_data14[79:0] rx_serdes_data15[79:0]	rx_serdes_data13[79:0]	rx_serdes_data7[79:0]
8	14	rx_serdes_data16[79:0] rx_serdes_data17[79:0]	rx_serdes_data14[79:0]	rx_serdes_data8[79:0]
9	15	rx_serdes_data18[79:0] rx_serdes_data19[79:0]	rx_serdes_data15[79:0]	rx_serdes_data9[79:0]
10	16	rx_serdes_data20[79:0] rx_serdes_data21[79:0]	rx_serdes_data16[79:0]	rx_serdes_data10[79:0]
11	17	rx_serdes_data22[79:0] rx_serdes_data23[79:0]	rx_serdes_data17[79:0]	rx_serdes_data11[79:0]
core_mode refers to `ctl_core_mode[1:0]`. intf_mode refers to `c0_ctl_rx_serdes_intf_mode[1:0]`. gearbox_mode refers to `c0_ctl_rx_gearbox_mode[1:0]`. This column represents the output of the ILKNF hard macro. This column includes consideration for programmable logic outside of the hard macro.

Note: The above RX bit ordering table contains two columns for the same configuration. In this configuration, the ILKN hard macro expects data on ports that lack symmetry with the ports used for the TX path. Programmable logic is used to provide symmetry with the TX path.