Synthesizing and Implementing the Example Design - 1.2 English

Versal ACAP Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)
Document ID
PG371
Release Date
2023-01-19
Version
1.2 English
To run synthesis and implementation on the example design in Vivado® Design Suite, perform the following steps:
  1. Go to the XCI file, right-click and select Open IP Example Design. A new Vivado tool window opens with the project name example_project in the project directory.
  2. In the Flow Navigator, click Run Synthesis > Run Implementation.
  3. A C File named ilknf_exdes_test.c is generated in the following folder: <project_name>/<project_name>.gen/sources_1/bd/<ip_name>_exdes_support/ip/<ip_name>_exdes_support_<ip_name>_core_0/sample_c_files. This file contains basic functions such as packet scheduling, alignment detection and statistics comparison and reporting.
Tip: Click Run Implementation first to run both synthesis and implementation. Click Generate Bitstream to run synthesis, implementation, and then bitstream.