Segmented AXI4-Stream Protocol - 1.2 English

Versal ACAP Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)

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1.2 English

This section describes the segmented AXI4-Stream protocol for the ILKNF subsystem.

The AXI4-Stream interface accepts packet-oriented data of an arbitrary length. It accepts data in either Packet Mode or Burst-Interleaved mode. The interface is very wide (up to 2048-bit) and thus very few packets are likely to have sizes that are multiples (or near multiples) of the user interface width. Consequently, the AXI4-Stream bus is divided into 128-bit segments, with multiple transfers presented in parallel during the same clock cycle. This permits a (previous) packet to end and a (new) packet to begin in the same clock cycle. Each segment has all the control signals associated with a complete 128-bit AXI4-Stream bus. Use of segments allows the AXI4-Stream bus to be highly utilized and provides high throughput through the ILKNF subsystem.

The size of the AXI4-Stream interface is configurable based on the setting of the c0_ctl_tx_axis_width[2:0] field of the CFG_C0_TX_OVERALL_REG register and the c0_ctl_rx_axis_width[2:0] field of the CFG_C0_RX_OVERALL_REG register.
Note: The widths for both directions need to match.

A segment has a width of 128 bits or 16 bytes. The number of segments available can be calculated by dividing the width of the AXI4-Stream bus by 128, the number of bits inside a segment. For example, a 2048-bit AXI4-Stream bus has 16 segments, a 1536-bit AXI4-Stream bus has 12 segments, a 1024-bit AXI4-Stream bus has eight segments, a 768-bit AXI4-Stream bus has six segments, and a 512-bit AXI4-Stream bus has four segments.