Receive Resets - 1.2 English

Versal ACAP Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)

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1.2 English
The receive resets in the ILKNF subsystem are as follows:
RX reset signal for the ILKNF subsystem. If asserted, this signal resets all RX path logic of the ILKNF subsystem including the RX lane logic. Internally, this reset signal is first synchronized to c0_core_clk. It is then synchronized (in parallel) to c0_axi_clk (to be used in protocol block for the ILKNF subsystem), rx_serdes_clk[0] (to be used in RX lane logic), and rx_alt_serdes_clk[0]. This reset signal is unused in FEC-only mode.
For RX lanes configured in Interlaken mode, rx_serdes_reset[0] is the reset signal for RX lane logic of the ILKNF subsystem. The rx_serdes_reset[0] signal should be held in reset until the transceiver PLL is locked and rx_serdes_clk[0] is stable. Internally, rx_serdes_reset[0] is synchronized (in parallel) to rx_serdes_clk[0] and rx_alt_serdes_clk[0] clocks. The rx_serdes_reset[5:1] signal is unused in this mode. For RX lanes configured in FEC-only mode, the rx_serdes_reset[5:0] signals are reset signals for six 100G FEC decoders. Both 50G decoder slices of a 100G FEC core share the same reset signal. The reset signal for each FEC core is synchronized (in parallel) to its corresponding rx_serdes_clk[5:0] and rx_alt_serdes_clk[5:0] clocks.