Interlaken Mode - 1.2 English

Versal ACAP Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)

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1.2 English

When configured for Interlaken mode, the ILKNF subsystem carries out the Protocol Layer and Framing Layer (that is, the lane logic) functions of the Interlaken protocol. The core is placed into Interlaken mode through the appropriate setting of the ctl_tx_fec_only_enable[1:0] field of the CFG_TX_FEC_ONLY_REG register and the ctl_rx_fec_only_enable[1:0] field of the CFG_RX_FEC_ONLY_REG register.

When operating in Interlaken mode, the use of FEC on the Interlaken lanes is controlled using the c0_ctl_tx_gearbox_mode[1:0] field of the CFG_C0_TX_OVERALL_REG register and the c0_ctl_rx_gearbox_mode[1:0] field of the CFG_C0_RX_OVERALL_REG register.

In addition, when using FEC for Interlaken, ensure that 100G RS(544,514) KP4 is enabled using the slice mode control of the corresponding FEC instances. For example, for the first FEC instance (that is, FEC0), this would be accomplished through the appropriate setting of the following fields and registers:
  • The ctl_tx_fec0_slice0_mode[1:0] field of the CFG_TX_FEC0_SLICE0_REG register.
  • The ctl_tx_fec0_slice1_mode[1:0] field of the CFG_TX_FEC0_SLICE1_REG register.
  • The ctl_rx_fec0_slice0_mode[1:0] field of the CFG_RX_FEC0_SLICE0_REG register.
  • The ctl_rx_fec0_slice1_mode[1:0] field of the CFG_RX_FEC0_SLICE1_REG register.
Note: A change in the above fields requires a reset to be issued after configuration is complete.