GT Transceiver (SerDes) Modes - 1.2 English

Versal ACAP Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)

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1.2 English

The ILKNF is capable of interfacing with the Xilinx® Versal® GTY and GTM transceivers through the programmable logic region.

The ILKNF has lane logic functions including gearbox, scrambling, lane alignment, and lane deskew. For this reason, the transceivers connected to the ILKNF must be configured to operate in RAW mode. The transceiver interface configuration is 40-bit, 80-bit, or 160-bit depending on the lane rate.

To change the transceiver interface setting, use the c0_ctl_tx_serdes_intf_mode[1:0] field of the CFG_C0_TX_OVERALL_REG register and the c0_ctl_rx_serdes_intf_mode[1:0] field of the CFG_C0_RX_OVERALL_REG register.