FEC-Only Mode - 1.2 English

Versal ACAP Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)

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1.2 English

When configured for FEC-only mode, the ILKNF subsystem carries out FEC encoding and FEC decoding functions instead of Interlaken functions. The core exposes up to six 100 Gb/s capable RS-FEC instances (decoder and encoder). Each 100 Gb/s capable RS-FEC instance can be configured as a 100 Gb/s RS-FEC decoder and encoder. Alternatively, it can be configured as two 50 Gb/s RS-FEC decoder/encoder pairs. Each of these 50 Gb/s decoder/encoder entities is known as a "slice" of an RS-FEC instance.

The core is placed into FEC-only mode through the appropriate setting of the ctl_tx_fec_only_enable[1:0] field of the CFG_TX_FEC_ONLY_REG register and the ctl_rx_fec_only_enable[1:0] field of the CFG_RX_FEC_ONLY_REG register.

A particular instance of the FEC is placed into 100 Gb/s (versus 2 x 50 Gb/s) mode using the slice mode control. For example, for the first FEC instance (that is, FEC0), this is accomplished through the appropriate setting of the following fields and registers:
  • The ctl_tx_fec0_slice0_mode[1:0] field of the CFG_TX_FEC0_SLICE0_REG register.
  • The ctl_tx_fec0_slice1_mode[1:0] field of the CFG_TX_FEC0_SLICE1_REG register.
  • The ctl_rx_fec0_slice0_mode[1:0] field of the CFG_RX_FEC0_SLICE0_REG register.
  • The ctl_rx_fec0_slice1_mode[1:0] field of the CFG_RX_FEC0_SLICE1_REG register.

When a FEC instance is configured in 2 x 50 Gb/s mode, you may choose to use one of the 50 Gb/s slices without using the other 50 Gb/s slice.