FEC-Only Clocking Modes - 1.2 English

Versal ACAP Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)

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1.2 English

In FEC-only mode, the core operates only in x2 width (that is, wide) mode to and from the user logic.

Each of the six 100 Gb/s capable FEC instances has its own set of clocks. For example, the first FEC instance (that is, FEC0) uses tx_alt_serdes_clk[0] in the TX path and rx_alt_serdes_clk[0] in the RX path. The data flowing between the user logic and ILKNF is clocked by these clocks. In addition, the tx_serdes_clk[0] (whose frequency is exactly double the tx_alt_serdes_clk[0] frequency) is passed into the ILKNF subsystem. Similarly, the rx_serdes_clk[0] (whose frequency is exactly double the rx_alt_serdes_clk[0] frequency) is also passed into the ILKNF subsystem. Internal to the ILKNF subsystem, the FEC logic uses the faster clocks.