Example Design Hierarchy - 1.2 English

Versal ACAP Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)

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1.2 English

The following shows the example design hierarchy of ILKNF. The IP is connected to multiple GT Quad base IPs depending upon the number of lanes chosen during the IP configuration. Each lane is connected to one channel of the GT quad. For more information on the GT Quad base IP, see the Versal ACAP Transceivers Wizard LogiCORE IP Product Guide (PG331).

Apart from the block design that connects ILKNF to GTs, the design consists of two more AXI4-Lite slaves namely the packet generator-monitor and the statistics and control register module.

Figure 1. Example Design Hierarchy