Control Ports - 1.2 English

Versal ACAP Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)

Document ID
Release Date
1.2 English

Besides configuration controls that are available through AXI4-Lite registers, the ILKNF IP provides dedicated ports for some controls. This allows user logic to drive these ports directly without going through the AXI4-Lite interface.

The following tables list the control ports. All control ports are inputs.

Table 1. TX Control Signal Descriptions
Port Name Clock Domain I/O Description
c0_ctl_tx_enable c0_axi_clk I TX enable. This signal is used to enable the transmission of data when it is sampled as a 1. When sampled as a 0, only IDLE control words (and the meta frame words) are transmitted by the ILKNF subsystem. This input should not be set to 1 until the receiver it is sending data to (the receiver in the other device) is fully aligned and ready to receive data. Otherwise, loss of data can occur. This input can be used for link-level flow control. For example, setting this input to 0 halts transmission of data and results in the entire link going into XOFF state.
c0_ctl_tx_fc_stat[255:0] c0_axi_clk I TX in-band flow control input. These signals are used to set the status for each calendar position in the in-band-flow control mechanism (see Interlaken Protocol Definition, Revision 1.2). A value of 1 means XON, a value of 0 means XOFF. These bits are transmitted in the Interlaken control word bits [55:40]. Each bit of c0_ctl_tx_fc_stat represents an entry in the flow control calendar with a length of 256 entries. When bit 56 of a control word is a value of 1, the first 16 calendar entries are output on bits 55-40. Specifically, bit 55 of the first control word reflects the state of c0_ctl_tx_fc_stat[0], bit 54 reflects the state of c0_ctl_tx_fc_stat[1], bit 53 reflects the state of c0_ctl_tx_fc_stat[2], and so on, as explained in section of the Interlaken specification. Subsequent control words contain the next 16 calendar entries and so forth.
c0_ctl_tx_mubits[7:0] c0_axi_clk I TX multiple-use control bits. This bus contains the multi-use field of the Interlaken control (see Interlaken Protocol Definition, Revision 1.2). The value of the bus is transmitted in the Interlaken control word bits [31:24] (for c0_ctl_tx_chan_ext=2’h0). You must define the function of this bus. If the bus is not used, set all bits to 0. When channel extension is used, transmitted mubits are as follows:
  • c0_ctl_tx_chan_ext=2’h0: c0_ctl_tx_mubits[7:0]
  • c0_ctl_tx_chan_ext=2’h1: c0_ctl_tx_mubits[6:0]
  • c0_ctl_tx_chan_ext=2’h2: c0_ctl_tx_mubits[5:0]
  • c0_ctl_tx_chan_ext=2’h3: c0_ctl_tx_mubits[4:0]
ctl_tx_diagword_lanestat[23:0] Async I Lane status messaging inputs. This bus sets bit 33 in the diagnostic word for the respective lane.
c0_ctl_tx_diagword_intfstat Async I Interface status messaging inputs. This signal sets bit 32 in the diagnostic word of each lane.
Table 2. RX Control Signal Descriptions
Port Name Clock Domain I/O Description
c0_ctl_rx_force_resync Async I RX resync input. This signal is used to force the RX lane logic of the ILKNF subsystem to reset, resynchronize, and realign. A value of 1 forces the reset operation. A value of 0 allows normal operation. This input should normally be low and should only be pulsed (one rx_serdes_clk[0] cycle minimum pulse) to force realignment.