AXI4-Lite Register Interface - 1.2 English

Versal ACAP Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)

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1.2 English
The ILKNF IP contains a soft logic 32-bit AXI4-Lite interface block to allow access to the APB3 interface of the integrated IP. Through the AXI4-Lite interface, you can access the internal configuration registers. For more details on the AXI4-Lite interface, see the AXI to APB Bridge LogiCORE IP Product Guide (PG073).
Table 1. AXI4-Lite Interface Signal Descriptions
Port Name I/O Description
s_axi_aclk I This clock is used for both the AXI4-Lite bridge soft logic and the ILKNF APB3 port clock.
Note: The s_axi_clk must be present for the ILKNF to function. If this clock is interrupted, the ILKNF IP enters an error state.
s_axi_areset I Active-High reset for the AXI4-Lite port. Asserting this reset alters the port control logic and stops any in-flight writes or reads. It does not reset the internal configuration registers, with exceptions listed below. |
s_axi_* I/O

See the AXI to APB Bridge LogiCORE IP Product Guide (PG073) and Vivado Design Suite: AXI Reference Guide (UG1037).

A complete description of the register map and the individual registers can be found in the Register Space section.