AXI4-Lite Clock and Reset - 1.2 English

Versal ACAP Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)

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1.2 English

The AXI4-Lite interface has its own clock and reset. The AXI4-Lite clock (s_axi_aclk) is independent of the remainder of the ILKNF clocks and can be any frequency to a maximum of 300 MHz.

Important: The AXI4-Lite clock must be present and stable for the ILKNF IP to operate. An interruption in the AXI4-Lite clock is likely to result in an unrecoverable internal ILKNF error. When the AXI4-Lite clock has returned and is stable, this requires a full reset-sequence to bring the ILKNF IP back to a stable condition.
Asserting the AXI4-Lite s_axi_areset pin results in the following:
  • A reset of the AXI4-Lite port and ILKNF APB3 control logic, stopping any in-flight writes or reads.
  • A reset of the soft reset registers found in CFG_C0_RESET_REG, CFG_TX_SERDES_RESET_REG and CFG_RX_SERDES_RESET_REG.

An AXI4-Lite reset does not reset the internal configuration registers.