User Interface - User Interface - 1.2 English - PG251

A simple handshaking protocol is used to alert you of the reception of pause packets using the ctl_rx_pause_enable[8:0], stat_rx_pause_req[8:0] and ctl_rx_pause_ack[8:0] buses. For these buses, bit [8] corresponds to global pause packets and bits [7:0] correspond to priority pause packets.

The following steps occur when a pause packet is received:

1. If the corresponding bit of ctl_rx_pause_enable[8:0] is 0, the quanta is ignored and the hard CMAC stays in step 1.
   Note: Otherwise, the corresponding bit of the stat_rx_pause_req[8:0] bus is set to 1, and the received quanta is loaded into a timer.
2. If ctl_rx_check_ack input is 1, the core waits for you to set the appropriate bit of the ctl_rx_pause_ack[8:0] bus to 1.
3. After you set the proper bit of ctl_rx_pause_ack[8:0] to 1, or if ctl_rx_check_ack is 0, the core starts counting down the timer.
4. When the timer times out, the core sets the appropriate bit of stat_rx_pause_req[8:0] back to 0.
5. If ctl_rx_check_ack input is 1, the operation is complete when you set the appropriate bit of ctl_rx_pause_ack[8:0] back to 0.

If you do not set the appropriate bit of ctl_rx_pause_ack[8:0] back to 0, the core deems the operation complete after 32 clock cycles.

These steps are demonstrated in the following figure with each step shown on the waveform.

Figure 1. RX Pause Interface Example

If at any time during Step 2 to Step 5 a new pause packet is received, the timer is loaded with the newly acquired quanta value and the process continues.