Port Descriptions - Port Descriptions - 1.2 English - PG251

USXGMII Ethernet Subsystem Product Guide (PG251)
Document_ID
PG251
Release_Date
2024-05-30
Version
1.2 English

The following table details the additional signals present when the packet timestamping feature is included.

Table 1. 1588v2 Port List and Descriptions
Name Direction Clock Domain Description
IEEE 1588 Interface – TX Path
ctl_tx_systemtimerin[79:0] Input tx_serdes_clk

System timer input for the TX. In normal clock mode, the 32 LSBs carry nsec and the 48 MSBs carry seconds. In transparent clock mode, bit 63 is expected to be zero, bits 62:16 carry nanoseconds, and bits 15:0 carry fractional nanoseconds. Refer to IEEE 1588v2 for the representational definitions.

This input must be in the TX SerDes clock domain.
tx_ptp_tstamp_valid_out Output tx_clk_out This bit indicates that a valid timestamp is being presented on the TX system interface.
tx_ptp_tstamp_tag_out[15:0] Output tx_clk_out Tag output corresponding to tx_ptp_tag_field_in[15:0]
tx_ptp_tstamp_out[79:0] Output tx_clk_out Timestamp for the transmitted packet SOP corresponding to the time at which it passed the capture plane. Time format same as timer input.
tx_ptp_1588op_in[1:0] Input tx_clk_out

The signal should be valid on the first cycle of the packet.

  • 2’b00 – No operation: no timestamp will be taken and the frame will not be modified.
  • 2’b10 – 2-step: a timestamp should be taken and returned to the client using the additional ports of 2-step operation. The frame itself will not be modified.
  • 2’b01 and 2’b11 – Reserved: act as No operation.
ctl_tx_ptp_1step_enable Input tx_clk_out This signal should be tied to 1’b0
ctl_ptp_transpclk_mode Input tx_clk_out When set to 1, this input places the timestamping logic into transparent clock mode.
tx_ptp_tag_field_in[15:0] Input tx_clk_out

The usage of this field is dependent on the 1588 operation. The signal should be valid on the first cycle of the packet.

  • For No operation, this field will be ignored.
  • For two-step this field is a tag field. This tag value will be returned to the client with the timestamp for the current frame using the additional ports of two-step operation. This tag value can be used by software to ensure that the timestamp can be matched with the PTP frame that it sent for transmission.
ctl_tx_ptp_latency_adjust[31:0] Input tx_clk_out

This bus can be used to adjust the one-step T timestamp with respect to the two-step timestamp.

Only the LSB 16-bits are used.
stat_tx_ptp_fifo_write_error Output tx_clk_out Transmit PTP FIFO write error. A value of 1 on this status indicates that an error occurred during the PTP Tag write. A TX Path reset is required to clear the error.
stat_tx_ptp_fifo_read_error Output tx_clk_out Transmit PTP FIFO read error. A value of 1 on this status indicates that an error occurred during the PTP Tag read. A TX Path reset is required to clear the error.
tx_ptp_rxtstamp_in Input tx_clk_out At present this port is not used. Should be tied to 0x0.
IEEE 1588 Interface – RX Path
ctl_rx_systemtimerin[79:0] Input rx_serdes_clk System timer input for the RX. Same time format as the TX. This input must be in the same clock domain as the RX SerDes.
rx_ptp_tstamp_out[79:0] Output rx_clk_out Timestamp for the received packet SOP corresponding to the time at which it passed the capture plane. This signal will be valid on the first cycle of the packet.