For transmit data
tx_axis_tdata[31:0], the port is logically divided into lane 0 to lane 3
as shown in the following table.
| Lane/tx_axis_tkeep | tx_axis_tdata[31:0] bits |
|---|---|
| 0 | 7:0 |
| 1 | 15:8 |
| 2 | 23:16 |
| 3 | 31:24 |
For transmit data
tx_axis_tdata[31:0], the port is logically divided into lane 0 to lane 3
as shown in the following table.
| Lane/tx_axis_tkeep | tx_axis_tdata[31:0] bits |
|---|---|
| 0 | 7:0 |
| 1 | 15:8 |
| 2 | 23:16 |
| 3 | 31:24 |