Core Overview - Core Overview - 1.2 English - PG251

USXGMII Ethernet Subsystem Product Guide (PG251)

Document_ID
PG251
Release_Date
2024-05-30
Version
1.2 English

The USXGMII IP Core provides an architecture to convey a single port of Ethernet over a 10GE BASE-R link in a way that maximizes existing standards and thus reduces risk. The port can operate at an effective data rate of 10M, 100M, 1GE, 2.5GE, 5GE, or 10GE. The IP core is implemented with a low-latency 32-bit datapath.

Typical applications include connecting to an electrical Copper PHY (10GBASE-T) application-specific standard products (ASSPs).

This product guide contains an overview of the USXGMII IP core as well as example application, and licensing.