In order to instantiate the AXI4-Lite interface to access the control and status registers of the USXGMII IP Core, enable the Include AXI4-Lite
checkbox in the Configuration
Tab of the Vivado IDE. This option enables the usxgmii_0_axi_if_top module (which contains usxgmii_0_pif_registers with the usxgmii_0_slave_2_ipif module). You can access the AXI4-Lite interface logic registers (control, status, and statistics) from the
usxgmii_0_pkt_gen_mon module.
This mode enables the following features:
- You can configure all the control (CTL) ports of the core through the AXI4-Lite interface. This operation is performed by writing to a set of address locations with the required data to the register map interface.
- You can access all the status and statistics registers from the core through the AXI4-Lite interface. This operation is performed by reading the address locations for the status and statistics registers through register map.
AXI4 Interface User Logic
The following sections provide the AXI4-Lite interface state machine control and ports.
User State Machine
The read and write through the AXI4-Lite slave module interface is controlled by a state machine as shown in the following figure.
Following is a functional description of each state.
- IDLE_STATE: By default the FSM will be in IDLE_STATE. When the
user_read_reqsignal becomes High, then it moves to the READ_STATE else if theuser_write_reqsignal is High, it moves to WRITE_STATE else it remains in IDLE_STATE. - WRITE_STATE: You provide S_AXI_AWVALID , S_AXI_AWADDR , S_AXI_WVALID , S_AXI_WDATA and S_AXI_WSTRB in this state to write to the register map through AXI. When S_AXI_BVALID and S_AXI_BREADY from the AXI slave are High, it moves to ACK_STATE. If any write operation happens in any illegal addresses, the S_AXI_BRESP [1:0] signal indicates 2'b10 that asserts the write error signal.
- READ_STATE: You provide S_AXI_ARVALID and S_AXI_ARADDR in this state to read from the register map through AXI. When S_AXI_RVALID and S_AXI_RREADY are High then it moves to ACK_STATE. If any read operation happens from any illegal addresses, the S_AXI_RRESP [1:0 ] signal indicates 2'b10 that asserts the read error signal.
- ACK_STATE: The state moves to IDLE_STATE.
| Name | Size | Direction | Description |
|---|---|---|---|
| S_AXI_ACLK | 1 | Input | AXI clock signal |
| S_AXI_ARESETN | 1 | Input | AXI active-Low synchronous reset |
| S_AXI_PM_TICK | 1 | Input | PM tick user input |
| S_AXI_AWADDR | 32 | Input | AXI write address |
| S_AXI_AWVALID | 1 | Input | AXI write address valid |
| S_AXI_AWREADY | 1 | Output | AXI write address ready |
| S_AXI_WDATA | 32 | Input | AXI write data |
| S_AXI_WSTRB | 4 | Input | AXI write strobe. This signal indicates which byte lanes hold valid data. |
| S_AXI_WVALID | 1 | Input | AXI write data valid. This signal indicates that valid write data and strobes are available. |
| S_AXI_WREADY | 1 | Output | AXI write data ready |
| S_AXI_BRESP | 2 | Output |
AXI write response. This signal indicates the status of the write transaction. ‘b00 = OKAY ‘b01 = EXOKAY ‘b10 = SLVERR ‘b11 = DECERR |
| S_AXI_BVALID | 1 | Output | AXI write response valid. This signal indicates that the channel is signaling a valid write response. |
| S_AXI_BREADY | 1 | Input | AXI write response ready. |
| S_AXI_ARADDR | 32 | Input | AXI read address |
| S_AXI_ARVALID | 1 | Input | AXI read address valid |
| S_AXI_ARREADY | 1 | Output | AXI read address ready |
| S_AXI_RDATA | 32 | Output | AXI read data issued by slave |
| S_AXI_RRESP | 2 | Output |
AXI read response. This signal indicates the status of the read transfer. ‘b00 = OKAY ‘b01 = EXOKAY ‘b10 = SLVERR ‘b11 = DECERR |
| S_AXI_RVALID | 1 | Output | AXI read data valid |
| S_AXI_RREADY | 1 | Input | AXI read ready. This signal indicates the user/master can accept the read data and response information. |