FEC-only Decoder I/F Ports for 100G Operation - 1.1 English

FEC-only Decoder I/F Ports for 100G Operation - 1.1 English - PG371

Versal ACAP Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)

Document ID

PG371

Release Date

2022-07-21

Version

1.1 English

In 100G mode, the bit ordering for the input of FEC0 decoder is as follows:

At the start of the codeword where rx_fec0_slice0_din_start=1,
- rx_serdes_data0[79:0]=CW[79:0]
- rx_serdes_data1[79:0]=CW[159:80]
- rx_serdes_data2[79:0]=CW[239:160]
- rx_serdes_data3[79:0]=CW[319:240]
At the second codeword cycle,
- rx_serdes_data0[79:0]=CW[399:320]
- rx_serdes_data1[79:0]=CW[479:400]
- rx_serdes_data2[79:0]=CW[559:480]
- rx_serdes_data3[79:0]=CW[639:560]
At the third codeword cycle,
- rx_serdes_data0[79:0]=CW[719:640]
- rx_serdes_data1[79:0]=CW[799:720]
- rx_serdes_data2[79:0]=CW[879:800]
- rx_serdes_data3[79:0]=CW[959:880]
At the 17th codeword cycle,
- rx_serdes_data0[79:0]=CW[5199:5120]
- rx_serdes_data1[79:0]=CW[5279:5200]
- rx_serdes_data2[79:0]=CW[5359:5280]
- rx_serdes_data3[79:0]=CW[5439:5360]

In 100G mode, the bit ordering for the output of FEC0 decoder is as follows:

At the start of the codeword where rx_fec0_slice0_dout_start=1,
- rx_fec0_slice0_dout[159:0]=CW[159:0]
- rx_fec0_slice1_dout[159:0]=CW[319:160]
At the second codeword cycle,
- rx_fec0_slice0_dout[159:0]=CW[479:320]
- rx_fec0_slice1_dout[159:0]=CW[639:480]
At the third codeword cycle,
- rx_fec0_slice0_dout[159:0]=CW[799:640]
- rx_fec0_slice1_dout[159:0]=CW[959:800]
At the 17th codeword cycle,
- rx_fec0_slice0_dout[159:0]=CW[5279:5120]
- rx_fec0_slice1_dout[159:0]=CW[5439:5280]

The bit ordering for all 100G decoder interfaces is similar to FEC0. See the following table for a summary of 100G decoder bit ordering.

Table 1. 100G Decoder FEC-Only Bit Ordering Summary
FEC Inst	Decoder Input	Input CW Start Position	Decoder Output	Output CW Start Position
FEC0	rx_serdes_data0[79:0] rx_serdes_data1[79:0] rx_serdes_data2[79:0] rx_serdes_data3[79:0]	rx_serdes_data0[0]	rx_fec0_slice0_dout[159:0] rx_fec0_slice1_dout[159:0]	rx_fec0_slice0_dout[0]
FEC1	rx_serdes_data4[79:0] rx_serdes_data5[79:0] rx_serdes_data6[79:0] rx_serdes_data7[79:0]	rx_serdes_data4[0]	rx_fec1_slice0_dout[159:0] rx_fec1_slice1_dout[159:0]	rx_fec1_slice0_dout[0]
FEC2	rx_serdes_data8[79:0] rx_serdes_data9[79:0] rx_serdes_data10[79:0] rx_serdes_data11[79:0]	rx_serdes_data8[0]	rx_fec2_slice0_dout[159:0] rx_fec2_slice1_dout[159:0]	rx_fec2_slice0_dout[0]
FEC3	rx_serdes_data12[79:0] rx_serdes_data13[79:0] rx_serdes_data14[79:0] rx_serdes_data15[79:0]	rx_serdes_data12[0]	rx_fec3_slice0_dout[159:0] rx_fec3_slice1_dout[159:0]	rx_fec3_slice0_dout[0]
FEC4	rx_serdes_data16[79:0] rx_serdes_data17[79:0] rx_serdes_data18[79:0] rx_serdes_data19[79:0]	rx_serdes_data16[0]	rx_fec4_slice0_dout[159:0] rx_fec4_slice1_dout[159:0]	rx_fec4_slice0_dout[0]
FEC5	rx_serdes_data20[79:0] rx_serdes_data21[79:0] rx_serdes_data22[79:0] rx_serdes_data23[79:0]	rx_serdes_data20[0]	rx_fec5_slice0_dout[159:0] rx_fec5_slice1_dout[159:0]	rx_fec5_slice0_dout[0]