Video Data - 1.1 English

The AXI4-Stream interface specification restricts TDATA width to integer multiples of 8 bits. Therefore, any bit data must be padded with zeros on the MSB to form a N*8 bit wide vector before connecting to s_axis_video_tdata . Padding does not affect the size of the core.

Similarly, data on the Gamma LUT output m_axis_video_tdata is packed and padded to multiples of 8 bits as necessary. Zero padding the most significant bits is only necessary for 10-bit wide data. This Figure and This Figure explain the pixel mapping of AXI4-Stream interface with 2 pixels per clock and 10 bits per component configuration for all supporting color formats. Zero padding (bits [63:60]) is not shown in the figures.

Figure 2-2: Dual Pixels per Clock, 10 bits per Component Mapping for RGB

X-Ref Target - Figure 2-2

Figure 2-3: Dual Pixels per Clock, 10 bits per Component Mapping for YUV 4:4:4

X-Ref Target - Figure 2-3