Synthesizable Example Design - 1.1 English

PG285 Gamma Look Up Table

Document ID
Release Date
1.1 English
Figure 5-2: Synthesizable Example Design

X-Ref Target - Figure 5-2


The difference between the synthesizable example design and the simulation example design is the use of the MicroBlaze microprocessor instead of the AXI VIP core as the AXI master. The locked port of AXI4-Stream to Video Out is connected to the axi_gpio_lock core and the MicroBlaze processor polls the corresponding register for a sign that the test has passed.

The synthesizable example design requires both Vivado® and the Xilinx® Vitis tools. The first step is to run synthesis, implementation, and bitstream generation in Vivado. After all those steps are done, select File -> Export -> Export Hardware . In the window, select Include bitstream , select an export directory and click OK .

The remaining work is performed in the Xilinx Vitis tool. The Gamma LUT example design file can be found in the Vitis directory:

(<install_directory>/ <release> /data/embeddedsw/XilinxProcessorIPLib/drivers/v_gamma_lut_v1_2/examples/

Example application design source files (contained within examples folder) are tightly coupled with the Gamma LUT example design available in the Vivado catalog.

The vgamma_lut_example.tcl file automates the process of generating the downloadable bit and .elf files from the provided example .xsa file. To run the provided Tcl script, perform the following steps:

1. Copy the exported example design .xsa file in the examples directory of the driver.

2. Launch the Xilinx Software Command-Line Tool ( xsct ) terminal.

3. Use cd to access the examples directory.

4. Source the Tcl file:

xsct%>source vgamma_lut_example.tcl

5. Execute the script:

xsct%>vgamma_lut_example <xsa_filename.xsa>

The Tcl script performs the following actions:

Creates workspace

Creates HW project

Creates BSP

Creates application project

Builds BSP and application project

After the process is complete, the required files are available in the following directories:

bit file -> vgamma_lut_example.sdk/vgamma_lut_example_hw_platform folder

elf file -> vgamma_lut_example.sdk/vgamma_lut_example_design/{Debug/Release} folder

Next, perform the following steps to run the software application:

IMPORTANT: To do so, make sure that the hardware is powered on and a Digilent Cable or an USB Platform Cable is connected to the host PC. Also, ensure that a USB cable is connected to the UART port of the KC705 board.

1. Launch the Vitis IDE.

2. Set workspace to vgamma_lut_example.sdk folder in prompted window. The Vitis project opens automatically. If a welcome page shows up, close that page.

3. Download the bitstream into the FPGA by selecting Xilinx Tools > Program FPGA . The Program FPGA dialog box opens.

4. Ensure that the Bitstream field shows the bitstream file generated by the Tcl script, and then click Program .

Note: The DONE LED on the board turns green if the programming is successful.

5. A terminal program (HyperTerminal or PuTTY) is needed for UART communication. Open the program, choose the appropriate port, set the baud rate to 115200, and establish a serial port connection.

6. Select and right-click the vgamma_lut_example_design application in the Project_Explorer panel.

7. Select Run As > Launch on Hardware (System Debugger).

8. Select Binaries and Qualifier in window and click OK . The example design test results are shown in terminal program.

For more information, visit .

When executed on the board, the example application performs the following actions:

Programs the video clock generator to 1080p@60 Hz

Programs TPG and Gamma LUT to 1080p@60 Hz

Checks for video lock and reports the status (PASS/FAIL) on UART

Repeats steps 1-3 for 4KP@30 Hz and 4KP@60 Hz