After synthesis, all logic and registers placed into the "source" SLR (where the AXI4-Stream master connected to the SI interface is located) contain the cell name pattern "*slr_source*". All logic and registers placed into the "destination" SLR (where the AXI4-Stream slave connected to the MI interface is located) contain the cell name pattern "*slr_dest*". Constraints that combine the instance name of the AXI4-Stream Register Slice and either of these sub-module name patterns can then be used to group all cells in the core into their respective PBLOCKs for floorplanning.
In the following example, an AXI4-Stream Register Slice instance named "my_reg" is constrained to cross a SLR boundary that exists in the target device between row Y4 (the top of the lower SLR) and row Y5 (the bottom of the upper SLR):
create_pblock master_slr
add_cells_to_pblock [get_pblocks master_slr] [get_cells -hierarchical -filter "NAME=~*my_reg*slr_source*"]
resize_pblock [get_pblocks master_slr] -add {CLOCKREGION_X0Y0:CLOCKREGION_X5Y4}
create_pblock slave_slr
add_cells_to_pblock [get_pblocks slave_slr] [get_cells -hierarchical -filter "NAME=~*my_reg*slr_dest*"]
resize_pblock [get_pblocks slave_slr] -add {CLOCKREGION_X0Y5:CLOCKREGION_X5Y9}