Revision History - 1.1 English

AXI4-Stream Infrastructure IP Suite (PG085)

Document ID
Release Date
1.1 English

The following table shows the revision history for this document.


Revision Summary

08/08/2022 Version 3.0

IP Facts

Added UltraScale+ and Versal architecture support.

Design Flow Steps

Updated remap string examples in the Extra Settings section.

11/17/2021 Version 3.0

 Designing with the Core

Updated Enable URAM Memory Type.

12/05/2018 Version 3.0

All chapters

Updated for AXI4-Stream Data FIFO core changes:

Added Xilinx Parameterized Macro support.

Updated FIFO depth support, and support for multiple clocks, ECC, various resource utilization types, and optional FIFO flags.

Removed FIFO Generator support.

04/04/2018 Version 2.2

Product Specification and Design Flow Steps

Updated AXI4-Stream Switch Arbiter Algorithm, AXI4-Steam Slice parameters, and core constraints.

1/29/2017 Version 2.2

Product Specification

Updated AXI4-Stream Register Slice to add user-selectable performance vs. area tradeoff and optional pipelining to cross SLRs in SSI devices.

04/05/2017 Version 2.2

Product Specification

Updated for Enable FIFO Count Ports section.

04/06/2016 Version 2.2

Product Specification

Updated AXI4-Stream Subset Converter section.

04/01/2015 Version 2.2

Product Specification

Updated AXI4-Stream Switch section.

10/01/2014 Version 2.2

Product Specification and Upgrading

Updated Table 2-6. Added Device Migration section.

12/18/2013 Version 2.2

All chapters

Added UltraScale Architecture support.

10/02/2013 Version 2.2

Example Design and Test Bench

Added Example Design and Test Bench chapters.

03/20/2013 Version 2.1

Product Specification and Debugging

Updated Tables 2-3 and 2-5 and revised Debugging appendix.

12/18/2012 Version 2.0


Updated for characterization numbers and added Debugging appendix.

10/16/2012 Version 1.0

Initial Xilinx release.