Resource Utilization - 1.1 English

AXI4-Stream Infrastructure IP Suite (PG085)

Document ID
PG085
Release Date
2022-08-08
Version
1.1 English

The resource utilization of each AXI4-Stream Infrastructure IP is primarily a function of the payload width of the stream. The payload width of the stream is calculated as the width of the TDATA, TSTRB, TKEEP, TLAST, TID, TDEST, and TUSER signals. For example, consider the design that has the following signal widths listed in Table: Signal Widths Used for Resource Utilization Estimation.

Table 2-2:      Signal Widths Used for Resource Utilization Estimation

AXI4-Stream Signal

Width

TDATA

64

TSTRB

8

TKEEP

8

TLAST

1

TID

5

TDEST

6

TUSER

8

Total (Wp)

100

The payload width WP is calculated as 64 + 8 + 8 + 1 + 5 + 6 + 8 = 100. The register slice works as a double buffer and is able to hold two AXI4-Stream transfers at one time. Therefore, a rough estimate of utilization can be achieved by multiplying the payload width by two. This signal configuration from Table: Signal Widths Used for Resource Utilization Estimation is used in Table:  as the basis for the resource utilizations of the individual modules on a Kintex-7 FPGA (xc7k325tffg900-1) using the Vivado synthesis tool. UltraScale™ results are expected to be similar to 7 series results.

Table 2-3:      Resource Utilization by Module Type

Module

Feature

LUTs

FFs

Block RAMs

AXI4-Stream Broadcaster

2 Master Interfaces

5

2

0

4 Master Interfaces

9

4

0

8 Master Interfaces

21

8

0

AXI4-Stream Clock Converter

Asynchronous

104

287

0

Synchronous 2:1

109

211

0

Synchronous 1:2

107

209

0

AXI4-Stream Combiner

2 Slave Interfaces

1

1

0

4 Slave Interfaces

2

1

0

8 Slave Interfaces

4

1

0

AXI4-Stream Data Width Converter

TDATA: 32 to 64 bits   (WP= 56 to WP=100)

35

164

0

TDATA: 32 to 128 bits (WP=56 to WP =188)

44

254

0

TDATA: 64 to 32 bits   (WP =100 to WP =56)

51

164

0

TDATA: 64 to 128 bits (WP =100 to WP =188)

35

296

0

TDATA: 128 to 32 bits (WP =188 to WP =56)

129

257

0

TDATA: 128 to 64 bits (WP =188 to WP =100)

75

296

0

AXI4-Stream Register Slice

Default

110

206

0

AXI4-Stream Subset Converter

No SI TREADY -> MI TREADY

105

198

0

AXI4-Stream Switch

1 slave interface x 2 master interfaces

123

216

0

1 slave interface x 4 master interfaces

130

220

0

2 slave interface x 1 master interfaces

68

13

0

2 slave interface x 2 master interfaces

376

454

0

4 slave interface x 1 master interfaces

133

27

0

4 slave interface x 4 master interfaces

1028

978

0