Required Constraints - 1.1 English

AXI4-Stream Infrastructure IP Suite (PG085)

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1.1 English

The AXI4-Stream Infrastructure IP does not generally require any additional timing constraints other than clock period constraints on its clocks inputs. When an asynchronous clock converter is utilized, the underlying Xilinx Parameterized Macro is instantiated and generates an internal constraint file to prevent timing paths crossing clock domains from causing false timing errors. Those constraints apply only to internal logic inside the AXI4-Stream Infrastructure IP and are automatically generated with the IP.