Features - 1.1 English

AXI4-Stream Infrastructure IP Suite (PG085)

Document ID

PG085

Release Date

2022-08-08

Version

1.1 English

Buffering Modules

•AXI4-Stream Clock Converter

Provides clock crossing logic to bridge two clock domains.

•AXI4-Stream Data FIFO

Provides depth of 16 or deeper buffering with support for multiple clocks, ECC, different resource utilization types and optional FIFO Flags.

•AXI4-Stream Register Slice

Creates timing isolation and pipelining master and slave using a two-deep register buffer.

Transform Modules

•AXI4-Stream Combiner

°Aggregates multiple narrow AXI4-Stream transfers in parallel into one master by splicing the TDATA bits together in to create an AXI4-Stream transfer with a wider output.

LogiCORE IP Facts Table
Core Specifics
Supported Device Family⁽¹⁾	Versal® ACAP, UltraScale+™ Architecture, UltraScale™ Architecture, 7 Series
Supported User Interfaces	AXI4-Stream, AXI4-Lite
Resources	See Table: Latency by Module Type.
Provided with Core
Design Files	Verilog RTL
Example Design	Verilog
Test Bench	Verilog
Constraints File	Xilinx Design Constraints (XDC)
Simulation Model	Behavioral Verilog
Supported S/W Driver	N/A
Tested Design Flows⁽²⁾
Design Entry	Vivado® Design Suite
Simulation	For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis	Vivado Synthesis
Support
Release Notes and Known Issues	Master Answer Record: N/A
All Vivado IP Change Logs	Master Vivado IP Change Logs: 72775
Xilinx Support web page
Notes: 1.For a complete listing of supported devices, see the Vivado IP Catalog. 2.For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.