This register is responsible for committing the MI selector values from the control register block to the AXI4-Stream Switch block. This register has a single bit that commits the change. The commit causes the AXI4-Stream switch to go into a soft reset for approximately 16 cycles. This register is self-clearing when the commit/reset is complete.
|
Name |
Bits |
Description |
|---|---|---|
|
Reserved |
0 |
Reserved |
|
REG_UPDATE |
1 |
Register Update. MUX registers are double buffered. Writing '1' updates the registers and issues a soft reset to the core (for approximately 16 cycles.) |
|
Reserved |
31:2 |
Reserved |