AXI4-Stream Interconnect - 1.1 English

AXI4-Stream Infrastructure IP Suite (PG085)

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1.1 English

Note:   AXI4-Stream Interconnect requires IP integrator.

This Figure shows the top-most AXI4-Stream Interconnect core block diagram. Inside the AXI4-Stream Interconnect, an AXI4-Stream Switch core routes traffic between the Slave Interfaces (SI) and Master Interfaces (MI). Along each pathway connecting a SI or MI to the Switch, an optional series of AXI4-Stream Infrastructure cores (couplers) can perform various conversion and buffering functions. The couplers include: AXI4-Stream Register Slice, AXI4-Stream Data FIFO, AXI4-Stream Clock Converter, AXI4-Stream Data Width Converter and AXI4-Stream Protocol Converter.

Figure 4-13:      AXI4-Stream Interconnect

X-Ref Target - Figure 4-13


The AXI4-Stream Interconnect core can be configured to have up to 16 Slave Interfaces (SI) and up to 16 Master Interfaces (MI). Each SI connects to one AXI4-Stream master device and accepts transfers from the connected master device. Each MI connects to one AXI4-Stream slave device and issues transfers to slave devices. At the center is the Switch core that routes transfers between the SI and MI. Along each of the pathways between an SI and the Switch, or between the Switch and an MI, there can be one or more AXI4-Stream infrastructure cores to perform various conversion and storage functions.

The Switch effectively splits the AXI4-Stream Interconnect core down the middle between the SI-related functional units (SI hemisphere) and the MI-related units (MI hemisphere). Where possible, Vivado system design tools automatically insert couplers into the SI or MI hemisphere to resolve differences in the configuration of the connected master and slave devices.