AXI4-Lite Interface Signals

AXI4-Lite Interface Signals - 1.1 English

AXI4-Stream Infrastructure IP Suite (PG085)

Document ID

PG085

Release Date

2022-08-08

Version

1.1 English

Table: Optional AXI4-Lite Interface Signals lists the signals associated with the optional AXI4-Lite control register interface. This interface is optional and only present on a subset of IPs.

Table 2-7: Optional AXI4-Lite Interface Signals
Signal⁽¹⁾	Direction	Description
s_axi_ctrl_aclk	Input	Clock signal. All inputs/outputs of this bus interface are rising edge aligned with this clock.
s_axi_ctrl_aresetn	Input	Active-Low synchronous reset signal
s_axi_ctrl_awalid	Input	Write address valid. This signal indicates that the channel is signaling valid write address.
s_axi_ctrl_awready	Output	Write address ready. This signal indicates that the slave is ready to accept an address.
s_axi_ctrl_awaddr	Input	Write address. The write address gives the address of the transaction.
s_axi_ctrl_wvalid	Input	Write valid. This signal indicates that valid write data are available.
s_axi_ctrl_wready	Output	Write ready. This signal indicates that the slave can accept the write data.
s_axi_ctrl_wdata	Input	Write data.
s_axi_ctrl_bvalid	Output	Write response valid. This signal indicates that the channel is signaling a valid write response.
s_axi_ctrl_bready	Input	Write response ready. This signal indicates that the master can accept a write response.
s_axi_ctrl_bresp	Output	Write response. This signal indicate the status of the write transaction.
s_axi_ctrl_arvalid	Input	Read address valid. This signal indicates that the channel is signaling valid read address.
s_axi_ctrl_arready	Output	Read address ready. This signal indicates that the slave is ready to accept an address.
s_axi_ctrl_araddr	Input	Read address. The read address gives the address of the transaction.
s_axi_ctrl_rvalid	Output	Read valid. This signal indicates that the channel is signaling the required read data.
s_axi_ctrl_rready	Input	Read ready. This signal indicates that the master can accept the read data and response information.
s_axi_ctrl_rdata	Output	Read data.
s_axi_ctrl_rresp	Output	Read response. This signal indicate the status of the read transfer.
Notes: 1.This signal description is taken from the Arm AMBA Protocol Specification.