User Software Management Interface Ports - 1.0 English

Cached DRAM Binary CAM LogiCORE IP Product Guide (PG427)

Document ID
PG427
Release Date
2023-10-18
Version
1.0 English

CDBCAM supports standard AXI4-Lite interface with user software. The interface supported parameters values are:

Table 1. User Software Management Interface
Port Name I/O Width Clock Description
s_axi_araddr I 13 s_axi_aclk AXI4-Lite read request address.
s_axi_aresetn I 1 Asynchronous reset (active_low). The reset input is synchronized internally to s_axi_aclk domains.
rst_busy O 1 s_axi_aclk Reset Busy is an active-high indicator that the core is currently in reset state.
s_axi_arvalid I 1 s_axi_aclk AXI4-Lite read request valid.
s_axi_awaddr I 13 s_axi_aclk AXI4-Lite write request address.
s_axi_awvalid I 1 s_axi_aclk AXI4-Lite address write request valid.
s_axi_bready I 1 s_axi_aclk AXI4-Lite write response ready.
s_axi_aclk I 1 AXI4-Lite interface clock.
s_axi_rready I 1 s_axi_aclk AXI4-Lite read response ready.
s_axi_wdata I 32 s_axi_aclk AXI4-Lite write request data.
s_axi_wvalid I 1 s_axi_aclk AXI4-Lite data write request valid.
s_axi_arready O 1 s_axi_aclk AXI4-Lite read request ready.
s_axi_awready O 1 s_axi_aclk AXI4-Lite address write request ready.
s_axi_bresp O 2 s_axi_aclk AXI4-Lite write response status.
s_axi_bvalid O 1 s_axi_aclk AXI4-Lite write response valid.
s_axi_rdata O 32 s_axi_aclk AXI4-Lite read response data.
s_axi_rresp O 2 s_axi_aclk AXI4-Lite read response status.
s_axi_rvalid O 1 s_axi_aclk AXI4-Lite read response valid.
s_axi_wready O 1 s_axi_aclk AXI4-Lite data write request ready.