Test Bench - 1.0 English - PG427

Cached DRAM Binary CAM LogiCORE IP Product Guide (PG427)

Document ID
PG427
Release Date
2023-10-18
Version
1.0 English

The following figure shows the configuration of the example design test bench.

Figure 1. Example Design Test Bench Configuration

The test bench of the example design contains the following:

  • An instance of the CDCAM IP core based on the user configuration settings selected.
  • An AXI4-Lite Master block (axi_lite_master.sv).
  • A Lookup Interface block (lookup_interface.sv).
  • Test bench generated Stimulus in stimulus_tasks.svh.
  • Clocks and reset generation logic.
  • Test bench control logic.