The CAM IP generator core provides a quick way to simulate and observe the behavior of the core by using the provided example design, which has a self-checking test bench that uses the System Verilog Direct Programming Interface (DPI). Refer to Section 35 of IEEE 1800-2017 for more information about the functionality.
Change the target simulator in the new example design Vivado project as follows:
- In the Flow Navigator, click Settings in the Project Manager section. The Settings window is displayed.
- In the Settings dialog box, select Simulation under Project Settings.
- Select the target simulator you want to use, as shown in the following
figure.
For encrypted RTL simulation, Questa simulator requires an additional elaboration option "
-inlineFactor=0
" to be set in Vivado. See the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313) for more details. - Verify that the compiled library location is set correctly and points to the correct pre-compiled simulation libraries for the simulator being used. See the Vivado Design Suite User Guide: Logic Simulation (UG900) for instructions on how to compile simulation libraries.
Note: When the example design for the CAM IP is
generated, a simulation SystemVerilog package file is also created with the name
<instance-name>_sim_pkg.sv
. This file
contains the SystemVerilog task create
which
contains the configuration settings used for this particular CAM IP instance.