For each clock domain an asynchronous reset is applied. CDBCAM synchronizes internally each reset to the corresponding clock domain. All resets are active-low.
At startup, all resets must be asserted simultaneously for a duration of at
least four cycles of the slowest of the CDBCAM clocks. The system is not ready to use until
the reset phase is finished (indicated by the rst_busy
output). The
rst_busy
output is high for approximately 30 clock cycles (slowest
clock).