Product Specification - 1.0 English

Cached DRAM Binary CAM LogiCORE IP Product Guide (PG427)

Document ID
PG427
Release Date
2023-10-18
Version
1.0 English

The functional block diagram of the core is shown in the following figure.

Figure 1. Cached DRAM Binary CAM Block Diagram

The CDBCAM core components are as follows:

BCAM cache sub-system (BCS)
  • BCS is on-chip memory based binary CAM, and it is an optional block. Its rate and number of stored entries is parameter defined. It stores frequently matched entries and retrieves the response based on their exact match with the search key. Keys that are not found are sent for lookup to DBCAM. Once the responses are returned from the DBCAM, they are reordered in the BCS based on the order of their corresponding keys.
  • CDBCAM request and response AXI4-Stream interfaces are connected to the BCS when cache is used or bypassed internally to the LI_req and LI_resp interfaces of the DBCAM when cache is not used.
DBCAM
An external DRAM based binary CAM. Inserts, updates, and deletes are performed using the software based CAM driver. Lookups are performed entirely in HW by comparing the search key with the stored key in DRAM.
LI_Req
Line Lookup Interface Request. AXI4S slave port, accepting lookup requests.
CCI
Cache Command Interface for issuing insert and delete commands towards BCS, AXI4S master port.
LI_Resp
Line Lookup Interface Response. AXI4S master port, providing lookup responses.
DBSI
CDBCAM SW interface, AXI4-Lite slave port.
DMI
DRAM Interface, AXI4 master port connects to an NoC NMU.
DRAM Subsystem
Provides access to external DRAM via AXI4 interface using Versal NoC.