Address translation between the CDBCAM and
external memory must be performed by the NoC. For example, for a design with DDR memory
the incoming address (0x0) from CDBCAM could
be remapped into DDR address region starting at 0x8_0000_0000.
The range for address remap should also be configured as per the required DRAM physical size for the design.
For designs involving HBM with multiple PCs, you should also configure address remap for all channels and range to the size of a single PC. Because there are two NMUs per PC, they need to be mapped to the same address range.
For more details see Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).